If both the inputs to the gate are LOW (0), the output displays a HIGH (1). If either of the inputs is HIGH (1), it yield a LOW at the output. The CMOS technology has been quite effectively used to implement various applications and logic functions. NOR gate is one such implementation, which can be done quite effectively using CMOS. In a static CMOS circuit, each gate output is always connected to Vdd or Vss through a low resistance path, as the circuit has a low resistance path between the output and the power rails. This results in somewhat more power consumption for the static circuit.
On the other hand in the dynamic state, the circuits make use of temporary storage of signal values on the capacitance of high impedance circuit nodes. This way the dynamic circuits have no static power dissipation. The transistor ME (Fig-2) eliminates static power consumption. The clock input (CLK) determines two phase operation of the circuit namely pre-charge and evaluation. After discharge during one cycle, the dynamic gate will wait for the next pre-charge pulse. As the pull down network remains OFF till it is required.
The switching speeds to happen to be faster in dynamic gates, as the load capacitance is reduced due to fewer numbers of transistors. For a static gate the fan-in of N requires 2N switching devices, but for a dynamic NOR gate we need to have only N+2 devices. The drawback in using capacitor CL is that the clock signal becomes a prerequisite to refresh the logic level. Clock signal ? (t) charges the up the load capacitance with the help of MP (P-Pre-charge) when a transition takes place from high to low; ME (E-Evaluate) is cut off and block any discharge path of CL through logic function transistors.
As the clock signal goes HIGH, MP is cut off, ME starts conducting, which in turn results in discharge of CL if one of the logic transistors has a high input. Though the dynamic CMOS gates have quite a few advantages like high noise margins, no static power consumption etc. while being used in logic circuits, but there are couple of disadvantages as well. For example, synchronising and timing the clock is quite an arduous task, designing the circuit is more complex. One of the key disadvantages of dynamic logic is that, it becomes very difficult to cascade multiple circuits, because;
¢ Input will go for a change only when O is low and it has to be stable during the period of high O. ¢ When O is low, the two or multiple stages in cascade are pre-charged to a high voltage. But, when O is high, it leads to some delay at the output of first stage, which in turn will lead to discharge of second and subsequent stage. In order to come over this advantage we make use of CMOS Domino logic. To this end an inverter is added for ensuring that the output remain low during pre-charge, thus prevent the next stage from evaluating, till such time the existing stage has finished evaluation.
This ensures that each stage at the output of the inverter can make at most one transition from LOW to HIGH. When there are multiple stages in cascade, evaluation continues from one stage to another which is equivalent to the dominos effect falling one after another. It is also worth emphasizing here that each gate requires an inverter, which in turn necessitates that we make use of more transistors. When it becomes somewhat impractical to implement dynamic CMOS gate, we can also convert a dynamic gate into a static gate, just by adding feedback pull-up.